1. Field of Invention
The present invention relates to a method of manufacturing integrated circuit devices. More particularly, the present invention relates to a method of manufacturing the memory cells and logic cells of an integrated circuit on a single silicon chip.
2. Description of Related Art
Embedded dynamic random access memory (DRAM) is a type of integrated circuit having both its memory cells and logic cells formed on a single silicon chip. Embedded DRAM is capable of transferring large quantity of data at a very high speed. Due to its high memory capacity and speed, embedded DRAM has been used inside high volume processing circuits, an example of which is a graphic processor. A complete embedded DRAM includes logic circuits, a transfer field effect transistor (transfer FET) and a capacitor coupled to the transfer FET. The transfer FET actually acts as a switch between the lower electrode of the capacitor and a bit line. Therefore, data within the capacitor can be written in or read out.
FIGS. 1A through 1E are schematic, cross-sectional views showing the progression of manufacturing steps in producing a conventional embedded DRAM. FIG. 1A is a schematic, cross-sectional view of the conventional embedded DRAM half way through the manufacturing process. On the right is a partially finished DRAM cell 170 while on the left is a partially finished logic transistor 172. The DRAM cells and the logic circuits of an embedded DRAM are formed above a substrate 100 on a single chip. Normally, the substrate is a P-type silicon substrate. In general, device isolation regions 102 are formed using a local oxidation of silicon (LOCOS) method. Alternatively, devices can be isolated by forming shallow trench isolation structures. Shallow trench isolation structures are formed by first etching out a trench, and then depositing oxide material into the trench using a chemical vapor deposition method.
In order to lower the resistivity of the gate layer, a layer of polysilicon and a layer of metallic silicide layer are deposited in sequence to form a polycide layer, and then the polycide layer is patterned. Alternatively, a polysilicon layer is first deposited over the substrate, then the polysilicon layer is patterned. Next, a metallic layer is deposited over the patterned polysilicon layer, and then a self-aligned silicide reaction is carried out to form metallic silicide layers above the polysilicon layer and the source/drain region at the same time.
However, using a self-aligned silicide process can lead to a shallow junction in the source/drain region, which can result in the generation of a large leakage current at the junction between capacitor and the source/drain region. Therefore, the gate layer of a DRAM cell comprises a polysilicon layer 112 and a metallic silicide layer. The metallic silicide layer on top of the source/drain region 124 is not formed by a self-aligned silicide process so that charge leakage can be avoided. On the other hand, the sheet resistance of the source/drain region 126 in the transistor of a logic circuit is normally lowered by forming a metallic silicide layer over the source-drain region 126 using a self-aligned silicide process.
Conventionally, the method of forming gate structures 104 and 106 includes, for example, forming an oxide layer over the substrate 100 using a thermal oxidation method. Then, a doped polysilicon layer, a tungsten silicide layer and a silicon nitride layer are sequentially formed over the oxide layer using a chemical vapor deposition method. Next, various layers are etched to form gate oxide layers 108 and 110, polysilicon layers 112 and 114, titanium silicide and metallic silicide layers 116 and 118, and silicon nitride gate cap layers 120 and 122. The source/drain regions 124 and 126 are formed by an impurity implantation using the gate cap layers 120 and 122 as masks.
Next, as shown in FIG. 1B, an annealing operation is carried out between 900.degree. C. to 1000.degree. C. Hence, the heat causes the dopants to diffuse evenly within the source/drain regions 124 and 126 to form source/drain regions 124a and 126a. Thereafter, spacers 128 and 130 are formed on the respective sidewalls of the gate structures 104 and 106. Then, the DRAM cell of the right is covered by an insulating layer 140.
Next, as shown in FIG. 1C, a self-aligned silicide process is performed to form a metallic silicide layer over the source/drain region 126. First, a refractory metallic layer 142 such as a titanium layer is formed over the substrate 100 using, for example, a physical vapor deposition method.
Next, as shown in FIG. 1D, the device is rapidly heated to about 700.degree. C. to 800.degree. C. for an annealing operation so that silicon in the source/drain region 126a reacts with metal in the metallic layer 142 to form a self-aligned silicide layer 150. Thereafter, unreacted titanium is removed by placing the substrate in a solution of hydrogen peroxide (H.sub.2 O.sub.2) and ammonia (NH.sub.4 OH) to carry out a wet etching operation. Finally, a second annealing operation is carried out to lower the resistivity of the metal silicide layer 150 above the source/drain region 126a.
Subsequently, as shown in FIG. 1E, a thick dielectric layer 152 is formed over the substrate 100, and then a contact opening 154 is formed in the dielectric layer 152 exposing the source/drain region 124a. Next, a conductive layer 156, a dielectric thin film 158 and another conductive layer 160 are sequentially formed above the substrate 100. Hence, a capacitor having electrical connection with the source/drain region 124a is formed.
In general, the logic circuit area and the memory cell area in an embedded DRAM have different gate structures. The gate of a DRAM cell normally comprises a tungsten silicide layer and a polysilicon layer, while the gate in a logic circuit area comprises a metal silicide layer and a polysilicon layer. Therefore, at least three masks must be used to pattern the DRAM gate and the logic gate. The number of masks used is closely related to the complexity of the manufacturing operation, reliability and yield rate. If the number of masking operations can be reduced, reliability and control of production can be increased and cost of production can be lowered.
In light of the foregoing, there is a need provide a better method of manufacturing embedded DRAMs.